`timescale 1ns/10ps
`define clock_period 20

module compare_2bit_tb;

	reg[1:0] a;
	reg[1:0] b;
	
	wire equal;

	compare_2bit compare_2bit_m1(
		.Equal(equal),
		.A(a),
		.B(b)
	);	
	
initial begin
	a <= 2'b00; b <= 2'b00; #(`clock_period * 10);
	a <= 2'b00; b <= 2'b01; #(`clock_period * 10);
	a <= 2'b00; b <= 2'b10; #(`clock_period * 10);
	a <= 2'b00; b <= 2'b11; #(`clock_period * 10);
	a <= 2'b01; b <= 2'b00; #(`clock_period * 10);
	a <= 2'b01; b <= 2'b01; #(`clock_period * 10);
	a <= 2'b01; b <= 2'b10; #(`clock_period * 10);
	a <= 2'b01; b <= 2'b11; #(`clock_period * 10);
	a <= 2'b10; b <= 2'b00; #(`clock_period * 10);
	a <= 2'b10; b <= 2'b01; #(`clock_period * 10);
	a <= 2'b10; b <= 2'b10; #(`clock_period * 10);
	a <= 2'b10; b <= 2'b11; #(`clock_period * 10);
	a <= 2'b11; b <= 2'b00; #(`clock_period * 10);
	a <= 2'b11; b <= 2'b01; #(`clock_period * 10);
	a <= 2'b11; b <= 2'b10; #(`clock_period * 10);
	a <= 2'b11; b <= 2'b11; #(`clock_period * 10);
	
	$stop;
	
end

endmodule
